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78M6610+PSU Data Sheet
5.5
Timing Specifications
5.5.1 RESET
1
5
Parameter
Reset pulse fall time
Reset pulse width
Condition
Min
–
–
Typ
1
1
Max
–
–
Unit
μ s
μ s
1
Guaranteed by design, not subject to test.
5.5.2 SPI Slave Port
Parameter
Condition
Min
Typ
Max
Unit
t SPIcyc
SPCK cycle time
1
–
–
μ s
t SPILead Enable lead time
15
–
–
ns
t SPILag
t SPIW
Enable lag time
SPCK pulse width:
High
0
250
–
–
–
–
ns
ns
Low
250
ns
2
t SPISCK SSB to first SPCK fall
Ignore if SPCK is low
when SSB falls.
–
1
–
ns
0
t SPIDIS
t SPIEV
t SPISU
t SPIH
Disable time
SPCK to Data Out (SDO)
Data input setup time (SDI)
Data input hold time (SDI)
–
10
5
1
–
–
–
–
25
–
–
ns
ns
ns
ns
1
Guaranteed by design, not subject to test.
SSB
SPCK
t SPILead
t SPIcyc
t SPILag
SDO
t SPISCK
t SPIW
MSB OUT
t SPIS U t SPI H
t SPIEV
t SPIW
LSB OUT
t SPIDIS
56
SDI
MSB IN
Figure 22: SPI Slave Port Timing
LSB IN
Rev 1
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